This invention relates to a signal loss detector for clock-data recovery circuitry of a high-speed serial interface, especially in a programmable logic device (PLD).
It has become common for PLDs to incorporate high-speed serial interfaces to accommodate high-speed (i.e., greater than 1 Gbps) serial input/output (I/O) standards. Many of these standards can operate at more than one clock rate. However, it is a common feature of most if not all high-speed serial data protocols that neither the clock nor information about the clock is sent with the data. Instead, the clock must be recovered from the data.
For this purpose, it is known to use “clock-data recovery” techniques in high-speed serial interfaces. Such techniques recover the clock from serial data using a closed-loop feedback system including, e.g., a phase-locked loop or delay-locked loop.
It should be apparent that any such data interface must be able to detect when it has lost its lock on the incoming data signal. For example, under the PCI-Express Generation II protocol (PCIe2), a receiver is required to flag signal loss when the input data amplitude is below 100 mV (peak-to-peak). Under PCIe2, the transceiver enters an idle state upon detecting signal loss. The transceiver further is required to exit, or recover, from the idle state quickly upon detecting an input signal above 100 mV (peak-to-peak). These requirements are challenging when using analog circuits, particularly considering that the data rate exceeds 1 Gbps and may be around 5 Gbps, and that the absolute magnitudes of signal voltages continue to decrease. For example, early signal detectors rectified the incoming signal with a diode, causing a voltage drop of 0.7 V (700 mV) which is much greater than the PCIe2 detection threshold. Even with more advanced analog detectors, which may include operational amplifiers instead of diodes, high-speed, low-voltage threshold detection is difficult.
Therefore, it has become common to use digital techniques to compare the incoming data to the set of possible legal data patterns, rather than relying on signal levels. If the data do not match any of those patterns, then the signal is considered to have been lost. Alternatively, or in addition, the signal may be compared to known illegal data patterns which, if present, indicate loss of signal.
However, in systems that include CDR circuitry, the CDR circuitry itself may output data with an apparent pattern which may mimic a legal data pattern. Indeed, that pattern may be suspect in most cases, but legal in other cases. For example, the phase detector in the loop circuit of CDR circuitry may output an alternating pattern of 1's and 0's, which is a suspect pattern because it may indicate that the circuit is caught in a loop, but which also is a legal pattern under the PCIe2 protocol. Therefore, an interface operating under PCIe2, for example, may not be able to detect loss of signal if it results in that pattern.
Accordingly, it would be desirable to be able to provide more reliable signal loss detection.